Engineering notes from the Fpgawright team
CDC detection, timing hazard analysis, tape-out economics, and the verification workflow decisions that matter — written by engineers who work on this problem daily.
Eliminating false positives in RTL linting
Generic RTL linters generate noise that teams learn to ignore — and then ignore the real violations too. How learned pattern weighting changes that without suppressing legitimate findings.
Timing hazard detection without full simulation
Static analysis catches a class of timing violations in minutes that simulation takes days to find — here's how the tradeoffs work.
How we learn from your bug history
The indexing model that turns your past tape-out incidents into first-class rules — and why it works better than manual weighting.
FPGA vs ASIC verification workflows
How static verification requirements differ between FPGA prototyping and ASIC tape-out — and how to configure Fpgawright for each.
Reducing tape-out respins
The economics of a respin — and the class of RTL violations that static analysis reliably catches before the mask is cut.
Clock domain crossing detection
A technical deep dive into how Fpgawright's CDC engine traces crossing paths, including reconvergence and multi-bit synchronization.
Integrating CI into hardware verification
Why hardware teams are adopting CI-first verification and how to set up Fpgawright in GitHub Actions and Jenkins in under an afternoon.
RTL code review best practices
What to look for in an RTL code review — and how static analysis changes the conversation from "what did we miss" to "what do we verify".
When simulation is not enough
Simulation coverage metrics look healthy until they don't — certain CDC paths, async resets, and FSM transitions are structurally invisible to stimulus-based verification. What static analysis finds that simulation can't.
The cost of a missed timing violation
How the cost of a timing violation compounds at each stage of the design cycle — from RTL to tape-out to silicon.
State machine coverage gaps
Why FSM unreachable states survive simulation — and how structural analysis finds them before they become field failures.
Design rule checks beyond sign-off
Design rule checks as a gate at sign-off catch violations too late to fix cheaply. Running the same checks from the first RTL commit changes the economics — and how engineers think about correctness while writing.