Fpgawright Documentation
Fpgawright catches design-rule violations and timing hazards in RTL code before tape-out — and gets sharper every cycle by learning from your team's historical fault patterns.
Where to start
If you're new to Fpgawright, begin with the Quickstart guide. You'll be running your first analysis in under 10 minutes.
Documentation sections
Quickstart
Installation, authentication, first analysis run, and CI hook setup. Start here if you're evaluating Fpgawright for the first time.
RTL Rules Reference
Complete reference for all 140+ design rules — organized by category with rule ID, description, severity, and example violations.
API Reference
REST API documentation for programmatic job submission, result retrieval, rule set configuration, and webhook setup.
RTL language support
- Verilog — IEEE 1364-2001 and IEEE 1364-2005
- SystemVerilog — IEEE 1800-2012 and IEEE 1800-2017
- VHDL — IEEE 1076 (beta in v0.9.2)
- Mixed-language designs are supported
CI integration
Native plugins are available for GitHub Actions, GitLab CI, and Jenkins. The GitHub Actions plugin posts inline PR comments on violation-introducing commits. See the CI integration guide for setup instructions.
Running into an issue? Email [email protected] — we respond within one business day for Team plan customers. If a rule is producing false positives on your architecture, include the rule ID and a minimal RTL example — we can tune or suppress it.