Pricing
Pricing that makes sense before your first tape-out
One prevented respin pays for years of Fpgawright. Evaluate free, scale when it sticks.
Starter
$0
forever
Evaluate Fpgawright on your own RTL. Up to 2 engineers.
2 seats / 5 design rule sets / 500 RTL file analyses per month
- Design rule violation detection
- Timing hazard flagging
- Basic report export (PDF)
- Community support
Most popular
Team
$490
per seat / month
For active verification teams running parallel design builds.
Up to 15 seats / unlimited rule sets / CI integration / custom bug-pattern learning
- Everything in Starter
- Custom rule sets per project
- Bug-pattern learning from historical tapeouts
- CI/CD pipeline integration (GitHub Actions, Jenkins)
- RTL diff analysis across design revisions
- Priority email support
Enterprise
Talk to us
For ASIC design houses and semiconductor teams with complex multi-project verification needs.
Unlimited seats / on-premise deployment option / SSO / SLA
- Everything in Team
- On-premise or private cloud deployment
- SSO / SAML integration
- Dedicated customer success
- Custom SLA and support agreement
- Multi-project design-rule inheritance
Common questions
Verilog (IEEE 1364), SystemVerilog (IEEE 1800), and VHDL. Mixed-language designs are supported.
Team plan uses our cloud. Enterprise includes on-premise or private cloud deployment.
You export your simulation failure logs and past bug reports in standard formats (CSV, JSON, or VCS log). Fpgawright's model indexes violation types, file paths, and module names to weight future analyses.
Yes. Every rule is individually toggleable via a YAML config file checked into your repo. Teams can also add custom rule assertions.
The Starter tier is permanently free up to 2 seats — no credit card, no expiry. Team access requires a brief application: we review each request to confirm Fpgawright fits your RTL stack and can give you accurate first-run results. If it's not the right fit, we'll tell you before onboarding.
No. Fpgawright is a static analysis tool — it does not simulate your design and it does not provide proof-of-correctness. It catches a specific class of structural RTL violations (CDC paths, reset topology errors, state machine coverage gaps, timing path issues) before you spend time in simulation finding them the hard way. Teams use it as a first-pass gate, not as a replacement for VCS, Questa, or formal tools like JasperGold.