Changelog
What's new in Fpgawright
Feature releases, rule additions, and integration updates.
v0.9.2
- Added VHDL support (beta) — IEEE 1076 parsing, CDC and reset rules
- New rule: GLT-018 — glitch path through combinational reconvergence
- GitHub Actions plugin v2.1 — supports matrix builds and parallel job execution
- Improved report rendering for designs with 4+ clock domains
v0.9.0
- Historical bug learning model — import VCS log format directly
- API v1.0 GA — webhooks for CI result posting, stable endpoint contract
- Diff-aware analysis: compare two commits or branches, report net-new violations only
- JSON export format for downstream tooling integration
v0.8.5
- Jenkins plugin initial release — works with Jenkins 2.440+
- 12 new reset topology rules (RST-011 through RST-022)
- Report export: JSON format added alongside existing PDF
- Performance improvement: 35% faster analysis on designs over 500k lines
v0.8.0
- Clock domain crossing engine v2 — handles 4+ clock domains with reconvergence detection
- Configuration via YAML file in repo root — rules, severity overrides, learning settings
- GitLab CI integration — native pipeline job definition
- Inline PR comments for GitHub — violation annotations on the diff view
v0.7.0
- Public beta launch — Starter tier available to all teams
- 140 base RTL rules coverage across 6 categories
- SystemVerilog IEEE 1800-2017 full parser support
- GitHub Actions plugin v1.0
- PDF report export with ranked violation list