RTL Rules Reference

Fpgawright ships with 140+ design rules organized into seven categories. All rules are enabled by default. Override severity or disable specific rules in your .fpgawright.yaml file.

Clock Domain Crossing (GLT)

Rules in this category detect unsafe clock domain crossing paths — the most common source of intermittent failures in mixed-frequency designs.

Rule ID	Description	Default
GLT-001	Unregistered signal crossing clock domains	ERROR
GLT-002	Multi-bit bus crossing without CDC synchronizer	ERROR
GLT-003	Reconvergence hazard — paths from same source through different domains	ERROR
GLT-004	Async reset propagation into synchronous domain	ERROR
GLT-005	Missing synchronizer FIFO on data path crossing	WARN
GLT-011	CDC path width mismatch at receiver	WARN
GLT-018	Glitch path through combinational reconvergence	ERROR

Reset Topology (RST)

Rules detecting incorrect reset handling — a common source of hard-to-reproduce boot failures and simulation mismatches.

Rule ID	Description	Default
RST-001	Async reset not de-asserted synchronously	ERROR
RST-002	Reset domain crossing without synchronizer	ERROR
RST-007	Asynchronous reset used in synchronous domain logic	ERROR
RST-012	Reset tree fanout exceeds threshold — potential glitch susceptibility	WARN
RST-015	Missing reset on registered output	WARN

State Machine Coverage (FSM)

Rules that trace finite state machine coverage against simulation logs and detect structural issues in state transition logic.

Rule ID	Description	Default
FSM-001	Unreachable state detected in state transition graph	ERROR
FSM-004	Missing default case in case statement	WARN
FSM-008	Latch inferred in state transition logic	ERROR
FSM-012	State not covered by simulation log (learning-assisted)	WARN
FSM-017	Missing transition assertion for critical path	WARN

Combinational Hazards (CMB)

Rules detecting combinational logic issues — latches, loops, false paths, and glitch-prone structures.

Rule ID	Description	Default
CMB-001	Unintended latch inferred from incomplete assignment	ERROR
CMB-005	Combinational loop detected in logic graph	ERROR
CMB-009	False path candidate not covered in timing constraints	WARN
CMB-016	Glitch-prone mux with unregistered select	WARN

Bus Width and Connectivity (BUS)

Rules detecting width mismatches, undriven inputs, and multi-driver conflicts.

Rule ID	Description	Default
BUS-001	Port width mismatch at module instantiation	ERROR
BUS-003	Undriven input port connected to logic	ERROR
BUS-007	Multiple drivers on same net	ERROR
BUS-011	Implicit port truncation — width assignment mismatch	WARN

Timing Path Analysis (TIM)

Static timing rules that identify setup/hold risks and long combinational paths without requiring full STA.

Rule ID	Description	Default
TIM-001	Setup violation risk — long combinational path between registers	WARN
TIM-004	Hold violation risk — zero-delay path between same-edge flip-flops	ERROR
TIM-009	Clock gating without enable synchronization	ERROR
TIM-015	Path length exceeds configured critical path budget	WARN

Configuring rules

Override severity or disable any rule in your .fpgawright.yaml:

rules:
  GLT-003: error   # default, explicit
  GLT-011: warn    # downgrade from error
  FSM-012: off     # disable entirely
  TIM-001:
    severity: warn
    threshold_ns: 4.5