Rule engine · Bug-pattern learning · CI integration

One static analysis pass. Every RTL violation ranked by what actually matters to your team.

How the rule engine, the learning model, and the diff-aware CI layer work together — and where each one fits in a real verification flow.

140+ design rules, tuned for real architectures

The base rule engine covers the violation classes verification engineers encounter in production silicon — not a generic linter checklist. Every rule maps to a specific failure mode with a known propagation path. This is not a style checker. These are the rules that, when violated, produce tape-out respins.

Clock Domain Crossing 28 rules covering async resets, multi-bit signals, reconvergence paths
Reset Topology 22 rules for synchronous vs. asynchronous reset handling and distribution
State Machine Coverage 18 rules detecting unreachable states, missing transitions, and missing assertions
Combinational Hazards 31 rules for glitch paths, latch inference, combinational loops, and false paths
Bus Width & Connectivity 24 rules for width mismatches, undriven inputs, and multi-driver conflicts
Timing Path Analysis 19 rules detecting setup/hold violations and long combinational paths

Rules are configurable via a YAML file in your repo root. Toggle individual rules on or off, adjust severity thresholds, and add custom rule assertions specific to your architecture.

.fpgawright.yaml 
rules:
  cdc:
    GLT-003: error
    GLT-011: warn
  reset:
    RST-007: error
learning:
  enabled: true
  weight_factor: 2.0
output:
  format: json
  fail_on: error

Your bug history, encoded as first-class rules

Export your simulation failure logs and past bug reports. Fpgawright's model indexes violation types, file paths, and module names. Violations that caused respins in past tapeouts are weighted at the top of every future report.

The learning model doesn't replace the base rule engine — it adjusts the ranking. If your architecture has a known pattern of CDC violations in a specific module family, that pattern rises. If a rule type has never fired on your codebase in 50k lines, its rank drops.

Set up learning
Fpgawright team learning configuration panel showing historical bug import interface with pattern weights

Works inside the tools your team already uses

Install in under 10 minutes. No new build system. No custom file format. Fpgawright reads standard Verilog, SystemVerilog, and VHDL from your existing repository layout.

GitHub Actions CI/CD integration
Jenkins CI/CD integration
GitLab CI CI/CD integration
Verilog / SystemVerilog IEEE 1364 / IEEE 1800-2017
VHDL IEEE 1076 support (beta)
REST API v1.0 GA — webhook support

Ranked, actionable, linkable

Every report is a ranked list of violations sorted by severity × learned weight. Each entry links to the file, line, and the relevant spec clause — or to your own prior incident if the learning model matched it.

Each violation entry includes:

  • Rule ID and human-readable description
  • File path, line number, and module context
  • Severity (error / warn) and learned weight score
  • Link to spec clause or your prior incident report
  • Export as PDF or JSON for downstream tooling
Request access
Fpgawright timing path analysis report showing setup and hold violation details with path annotations

Fpgawright doesn't replace your simulator. It tells you what to simulate first.

Request access Read the quickstart